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NCN4555 1.8V / 3V SIM Card Power Supply and Level Shifter
The NCN4555 is a level shifter analog circuit designed to translate the voltages between a SIM Card and an external microcontroller or MPU. A built-in LDO-type DC-DC converter makes the NCN4555 useable to drive 1.8 V and 3.0 V SIM card. The device fulfills the ISO7816-3 smart card interface standard as well as GSM 11.11 and related (11.12 and 11.18) and 3G mobile requirements (IMT-2000/3G TS 31.101). With the STOP pin a low current shutdown mode can be activated making the battery life longer. The Card power supply voltage (SIM_VCC) is selected using a single pin (MOD_VCC).
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QFN-16 MN SUFFIX CASE 488AK
* * * * * * * * * * *
Typical Applications
SIM Card Interface Circuit for 2G, 2.5G and 3G Mobile Phones Identification Module Smart Card Readers Wireless PC Cards
1.8 V to 5.5 V 2.7 V to 5.5 V
0.1mF 0.1mF GND 3 1 P3 P2 P1 P0 2 14 13 15
A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
VBB MPU or Microcontroller
5 1 2 3 4 VCC GND RST CLK I/O C4 C8 DET 1mF GND DET 5 6 7 8
ORDERING INFORMATION
Device NCN4555MN NCN4555MNG NCN4555MNR2 NCN4555MNR2G Package QFN-16 QFN-16 (Pb-Free) QFN-16 QFN-16 (Pb-Free) Shipping 123 Units / Rail 123 Units / Rail 3000/Tape & Reel 3000/Tape & Reel 7
VDD MOD_VCC RST CLK I/O GND 10 NCN4555 STOP
SIM_VCC
SIM_RST SIM_CLK SIM_I/O
9 11 8
SIM Card Detect GND
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Figure 1. Typical Interface Application
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
March, 2006 - Rev. 1
CCC CCC
Supports 1.8 V or 3.0 V Operating SIM Card The LDO is able to Supply More than 50 mA under 1.8 V and 3.0 V Built-in Pullup Resistor for I/O Pin in Both Directions All Pins are Fully ESD Protected According to ISO-7816 Specifications - ESD Protection on SIM Pins in Excess of 7 kV (Human Body Model) Supports up to More than 5 MHz Clock Low-Profile 3x3 QFN-16 Package Pb-Free Packages are Available*
MARKING DIAGRAM
16 1
NCN 4555 ALYWG G
Publication Order Number: NCN4555/D
NCN4555
NC 16 STOP MOD_VCC VDD NC I/O 15 RST CLK 14 13 Exposed Pad (EP)
1 2 NCN4555 3 4 5 6 7 8
12 11 10 9
NC SIM_CLK GND SIM_RST
VBAT NC SIM_VCC SIM_I/O
Figure 2. QFN-16 Pinout (Top View)
VBAT (2.7 V to 5.5 V) 5
STOP 1
50 mA LDO 1.8 V/3.0 V
7 SIM_VCC
MOD_VCC 2 VDD (1.8 V to 5.5 V) 3 RST 14
GND
9 SIM_RST
GND CLK 13 11 SIM_CLK
GND 14 kW DATA I/O
GND
18 kW I/O 15 DATA
I/O
8 SIM_I/O
GND GND 10 GND
Figure 3. NCN4555 Block Diagram
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NCN4555
PIN DESCRIPTIONS
PIN 1 Name STOP Type INPUT Description Power Down Mode pin: STOP = Low Low current shutdown mode activated STOP = High Normal Operation A Low level on this pin resets the SIM interface, switching off the SIM_VCC. The signal present on this pin programs the SIM_VCC value: MOD_VCC = Low SIM_VCC = 1.8 V MOD_VCC = High SIM_VCC = 3 V This pin is connected to the system controller power supply. It configures the level shifter input stage to accept the signals coming from the microprocessor. A 0.1 mF capacitor shall be used to bypass the power supply voltage. When VDD is below 1.1 V typical the SIM_VCC is disabled. The NCN4555 comes into a shutdown mode. No Connect POWER DC-DC converter supply input. The input voltage ranges from 2.7V up to 5.5V. This pin has to be bypass by a 0.1 mF capacitor. No Connect POWER This pin is connected to the SIM card power supply pin. An internal LDO converter is programmable by the external MPU to supply either 1.8 V or 3.0 V output voltage. An external 1.0 mF minimum ceramic capacitor recommended must be connected across SIM_VCC and GND. During a normal operation, the SIM_VCC voltage can be set to 1.8 V followed by a 3.0 V value, or can start directly to any of these two values. This pin handles the connection to the serial I/O of the card connector. A bidirectional level translator adapts the serial I/O signal between the card and the micro controller. A 14 kW (typical) pullup resistor provides a High impedance state for the SIM card I/O link. This pin is connected to the RESET pin of the card connector. A level translator adapts the external Reset (RST) signal to the SIM card. This pin is the GROUND reference for the integrated circuit and associated signals. Care must be taken to avoid voltage spikes when the device operates in a normal operation. This pin is connected to the CLOCK pin of the card connector. The CLOCK (CLK) signal comes from the external clock generator, the internal level shifter being used to adapt the voltage defined for the SIM_VCC. No Connect INPUT The clock signal, coming from the external controller, must have a Duty Cycle within the Min/Max values defined by the specification (typically 50%). The built-in level shifter translates the input signal to the external SIM card CLK input. The RESET signal present at this pin is connected to the SIM card through the internal level shifter which translates the level according to the SIM_VCC programmed value. This pin is connected to an external microcontroller or cellular phone management unit. A bidirectional level translator adapts the serial I/O signal between the smart card and the external controller. A built-in constant 18 kW (typical) resistor provides a high impedance state when not activated. No Connect
2
MOD_VCC
INPUT
3
VDD
POWER
4 5 6 7
NC VBAT NC SIM_VCC
8
SIM_I/O
INPUT/ OUTPUT OUTPUT GROUND OUTPUT
9 10 11
SIM_RST GND SIM_CLK
12 13
NC CLK
14 15
RST I/O
INPUT INPUT/ OUTPUT
16
NC
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NCN4555
ATTRIBUTES
Characteristics ESD protection HBM, SIM card pins (7, 8, 9, 10 & 11) (Note 1) HBM, All other pins (Note 1) MM, SIM card pins (7, 8, 9, 10 & 11) (Note 2) MM, All other pins (Note 2) CDM, SIM card pins (7, 8, 9, 10 & 11) (Note 3) CDM , All other pins (Note 3) Moisture sensitivity (Note 4) QFN-16 Flammability Rating Oxygen Index: 28 to 34 Values > 7 kV > 2 kV > 600 V > 200 V > 2 kV > 600 V Level 1 UL 94 V-0 @ 0.125 in
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. 2. 3. 4. Human Body Model, R =1500 W, C = 100 pF. Machine Model. CDM, Charged Device Model. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 5)
Rating LDO Power Supply Voltage Power Supply from Microcontroller Side External Card Power Supply Digital Input Pins Symbol VBAT VDD SIM_VCC Vin Iin Digital Output Pins Vout Iout SIM card Output Pins Vout Iout QFN-16 Low Profile package Power Dissipation @ TA = + 85C Thermal Resistance Junction-to-Air Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range PD RqJA TA TJ TJmax Tstg Value -0.5 VBAT 6 -0.5 VDD 6 -0.5 SIM_VCC 6 -0.5 Vin VDD + 0.5 but < 6.0 5 -0.5 Vout VDD + 0.5 but < 6.0 10 -0.5 Vout SIM_VCC + 0.5 but < 6.0 15 (internally limited) 440 90 -25 to +85 -25 to +125 +125 -65 to + 150 Unit V V V V mA V mA V mA mW C/W C C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 5. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25C
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NCN4555
POWER SUPPLY SECTION (-25C to +85C)
Pin 5 5 5 3 3 3 3 7 Symbol VBAT I VBAT I VBAT_SD VDD IVDD IVDD_SD VDD SIM_VCC Power Supply Operating current - ICC = 0 mA (Note 6) Shutdown current - STOP= Low (Note 7) Operating Voltage Operating Current - fCLK = 1 MHz (Note 8) Shutdown Current - STOP = Low Undervoltage Lockout MOD_VCC = High, VBAT = 3.0 V, ISIM_VCC = 50 mA MOD_VCC = High, VBAT = 3.3 V to 5.5 V, ISIM_VCC = 0 mA to 50 mA MOD_VCC = Low, VBAT = 2.7 V to 5.5 V, ISIM_VCC = 0 mA to 50 mA Short -Circuit Current - SIM_VCC shorted to ground , TA=25C 0.6 2.8 1.7 2.8 3.0 1.8 1.8 7.0 Rating Min 2.7 22 Typ Max 5.5 30 3.0 5.5 12 1.0 1.5 3.2 1.9 175 Unit V mA mA V mA mA V V V V mA
7
ISIM_VCC_SC
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. As long as VBAT - VDD v 2.5 V. For VBAT - VDD > 2.5 V the maximum value increases up to 35 mA (typical being in the +25 mA range). 7. As long as VBAT - VDD v 2.5 V. 8. Guaranteed by design over the operating temperature range specified.
DIGITAL INPUT/OUTPUT SECTION CLOCK, RESET, I/O, STOP, MOD_VCC
Pin 1,2, 13, 14, 15 13, 14 1, 2 15 Symbol Vin IIH & IIL VIH VIL VIH VIL VOH_I/O VOL_I/O IIH IIL Rpu_I/O Rating Input Voltage Range (STOP, MOD_VCC, RST, CLK, I/O) Input Current (STOP, MOD_VCC, RST, CLK) High Level Input Voltage (RST, CLK) Low Level Input Voltage (RST, CLK) High Level Input Voltage (STOP, MOD_VCC) Low Level Input Voltage (STOP, MOD_VCC) High Level Output Voltage (SIM_I/O = SIM_VCC, IOH_I/O = -20 mA) Low Level Output Voltage (SIM_I/O = 0 V, IOH_I/O = 200 mA) High Level Input Current (I/O) Low Level Input Current (I/O) I/0 Pullup Resistor Min 0 -100 0.7 * VDD 0.7 * VDD 0 0.7 * VDD 0 -20 12 18 Typ Max VDD 100 VDD 0.2 * VDD VDD 0.4 VDD 0.4 20 1.0 24 Unit V nA V V V V V V mA mA kW
15
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
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NCN4555
SIM INTERFACE SECTION (Note 9)
Pin 9 Symbol SIM_RST Rating SIM_VCC = +3.0 V (MOD_VCC = High) Output RESET VOH @ Isim_rst = -20 mA Output RESET VOL @ Isim_rst = +200 mA Output RESET Rise Time @ Cout = 30 pF Output RESET Fall Time @ Cout = 30 pF SIM_VCC = +1.8 V (MOD_VCC = Low) Output RESET VOH @ Isim_rst = -20 mA Output RESET VOL @ Isim_rst = +200 mA Output RESET Rise Time @ Cout = 30 pF Output RESET Fall Time @ Cout = 30 pF 11 SIM_CLK SIM_VCC = +3.0 V (MOD_VCC = High) Output Duty Cycle Max Output Frequency Output VOH @ Isim_clk = -20 mA Output VOL @ Isim_clk = +200 mA Output SIM_CLK Rise Time @ Cout = 30 pF Output SIM_CLK Fall Time @ Cout = 30 pF SIM_VCC = +1.8 V (MOD_VCC = Low) Output Duty Cycle Max Output Frequency Output VOH @ Isim_clk = -20 mA Output VOL @ Isim_clk = +200 mA Output SIM_CLK Rise Time @ Cout = 30 pF Output SIM_CLK Fall Time @ Cout = 30 pF 8 SIM_I/O SIM_VCC = +3.0 V (MOD_VCC = High) Output VOH @ ISIM_IO = -20 mA, VI/O = VDD Output VOL @ ISIM_IO = +1 mA, VI/O = 0 V SIM_I/O Rise Time @ Cout = 30 pF SIM_I/O Fall Time @ Cout = 30 pF SIM_VCC = +1.8 V (MOD_VCC = High) Output VOH @ ISIM_IO = -20 mA, VI/O =VDD Output VOL @ ISIM_IO = +1.0 mA, VI/O = 0 V SIM_I/O Rise Time @ Cout = 30 pF SIM_I/O Fall Time @ Cout = 30 pF 8 Rpu_SIM_I/O Card I/O Pullup Resistor Min 0.9 * SIM_VCC 0 Typ Max SIM_VCC 0.4 1 1 SIM_VCC 0.4 1 1 Unit V V ms ms
0.9 * SIM_VCC 0
V V ms ms % MHz V V ns ns % MHz V V ns ns V V ms ms V V ms ms kW
40 5 0.9 * SIM_VCC 0
60 SIM_VCC 0.4 18 18 60 SIM_VCC 0.4 18 18 SIM_VCC 0.4 1 1 SIM_VCC 0.3 1 1 14 18
40 5 0.9 * SIM_VCC 0
0.8 * SIM_VCC 0
0.8 * SIM_VCC 0
10
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. All the dynamic specifications (AC specifications) are guaranteed by design over the operating temperature range.
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NCN4555
TYPICAL CHARACTERISTICS
100 VBAT = 5.5 V 90 IVCC_SC_1.8 V (mA) IVCC_SC_3.0 V (mA) 90 100 VBAT = 5.5 V
80
80
70 VBAT = 2.7 V
70
VBAT = 3.3 V
60
60
50 -50
-30
-10
10
30
50
70
90
50 -50
-30
-10
10
30
50
70
90
TEMPERATURE (C)
TEMPERATURE (C)
Figure 4. Short Circuit Current IVCC_SC vs Temperature at SIM_VCC = 1.8 V (MOD_VCC = LOW)
30 VBAT = 3.3 V 25 VBAT = 5.5 V 20
Figure 5. Short Circuit Current IVCC_SC vs Temperature at SIM_VCC = 3.0 V (MOD_VCC = HIGH)
30
IVCC_SC_3.0 V (mA)
IVCC_SC_1.8 V (mA)
25
VBAT = 2.7 V VBAT = 5.5 V
20
15
15
10 -50
-30
-10 10 30 50 TEMPERATURE (C)
70
90
10 -50
-30
-10
10 30 50 TEMPERATURE (C)
70
90
Figure 6. IBAT vs temperature at 3.0 V
Figure 7. IVBAT vs Temperature at 1.8 V
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NCN4555
APPLICATION INFORMATION
CARD SUPPLY CONVERTER
The NCN4555 interface DC-DC converter is a Low Dropout Voltage Regulator capable of suppling a current in excess of 50 mA under 1.8 V or 3.0 V. This device features a very low quiescent current typically lower than 25 mA (Figure 6 and 7). MOD_VCC is a select input allowing a logic level signal to select a regulated voltage of 1.8 V (MOD_VCC = LOW) or 3.0 V (MOD_VCC = HIGH). Additionally, the NCN4555 has a shutdown input allowing it to turn off or turn on the regulator output. The shutdown mode power consumption is typically in the range of a few tens of nA (30 nA Typical). Figure 8 shows a simplified view of the NCN4555 voltage regulator. The SIM_VCC output is internally current limited and protected against short circuits. The short-circuit current IVCC is constant over the temperature and SIM_VCC. It varies with VBAT typically in the range of 60 mA to 90 mA (Figure 4 and 5).
In order to guarantee a stable and satisfying operating of the LDO the SIM_VCC output will be connected to a 1.0 mF bypass ceramic capacitor to the ground. At the input, VBAT will be bypassed to the ground with a 0.1 mF ceramic capacitor.
LEVEL SHIFTERS
The level shifters accommodate the voltage difference that might exist between the microcontroller and the smart card. The RESET and CLOCK level shifters are monodirectional and feature both the same architecture. The bidirectional I/O line provides a way to automatically adapt the voltage difference between the MCU and the SIM card in both directions. In addition with the pullup resistor, an active pullup circuit (Figure 8, Q1 and Q2) provides a fast charge of the stray capacitance, yielding a rise time fully within the ISO7816 specifications.
VBAT Ilim R1
SIM_VCC
Q1
CIN = 0.1 mF
STOP
Figure 8. Simplified Block Diagram of the LDO Voltage Regulator
VDD SIM_VCC
Q1 18 k 200 ns 200 ns
I/O
IO/CONTROL
LOGIC
Figure 9. Basic I/O Line Interface http://onsemi.com
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+ + VREF R2 GND Q2 14 k GND Q3 GND
- COUT = 1.0 mF MOD_VCC SIM_I/O
NCN4555
The typical waveform provided in Figure 10 shows how the accelerator operates. During the first 200 ns (typical), the slope of the rise time is solely a function of the pullup resistor associated with the stray capacitance. During this period, the PMOS devices are not activated since the input voltage is below their Vgs threshold. When the input slope crosses the Vgsth, the opposite one shot is activated, providing a low impedance to charge the capacitance, thus increasing the rise time as depicted in Figure 10. The same mechanism applies for the opposite side of the line to make sure the system is optimum.
INPUT SCHMITT TRIGGERS ESD PROTECTION
The NCN4555 SIM interface features an HBM ESD voltage protection in excess of 7 kV for all the SIM pins (SIM_IO, SIM_CLK, SIM_RST, SIM_VCC and GND). All the other pins (microcontroller side) sustain at least 2 kV. These values are guaranteed for the device in its full integrity without considering the external capacitors added to the circuit for a proper operating. Consequently in the operating conditions it is able to sustain much more than 7 kV on its SIM pins making it perfectly protected against electrostatic discharge well over the HBM ESD voltages required by the ISO7816 standard (4 kV).
PRINTED CIRCUIT BOARD LAYOUT
All the Logic input pins (excepted I/O and SIM_I/O, See Figure 3) have built-in Schmitt trigger circuits to prevent the NCN4555 against uncontrolled operation. The typical dynamic characteristics of the related pins are depicted Figure 11. The output signal is guaranteed to go High when the input voltage is above 0.7 x VDD, and will go Low when the input voltage is below 0.2 x VDD or 0.4 V depending on the input considered (see the Digital Input Table on page 5).
SHUTDOWN OPERATING
In order to save power or for other purpose required by the application it is possible to put the NCN4555 in a shutdown mode by setting Low the pin STOP. On the other hand the device enters automatically in a shutdown mode when VDD becomes lower than 1.1 V typically.
Careful layout routing will be applied to achieve a good and efficient operating of the device in its mobile or portable environment and fully exploit its performance. The bypass capacitors have to be connected as close as possible to the device pins (SIM_VCC, VDD or VBAT) in order to reduce as much as possible parasitic behaviors (ripple and noise). It is recommended to use ceramic capacitors. The exposed pad of the QFN-16 package will be connected to the ground as well as the unconnected pins (NC). A relatively large ground plane is recommended. Figures 12 and 13 shows an example of PCB device implementation in an evaluation environment.
OUTPUT
VDD
ON
OFF INPUT 0.2 x VDD or 0.4 V 0.7 x VDD
Figure 10. SIM_IO Typical Rise and Fall Times with Stray Capacitance > 30 pF (33 pF Capacitor Connected on the Board)
Figure 11. Typical Schmitt Trigger Characteristics
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GND
J1 STOP MOD IP4 IP5 1 2 D3 3 VDD SIM_CLK 11 9SIM_RST 8 SIM_I/O 10 GND 6 7 SIM_VCC J8 NC 12 1 V2 VDD C2 10 mF SIM_I/O IP8 1 1 1 1 1 SIM_CLK SIM_RST IP6 IP7
CLK 1 1
CLK RST I/O IP1 IP2 IP3
VDD IP10
1
GND MBRA140T3 VDD R2 VBAT D4 2 100 nF 1 C1 1 D1 R1 2.2 k VBAT 10 k R3 2 STOP 1 S1 S2 NC NC NC NC NC MOD_VCC 1 V1 VBAT 2 10 k
J2
RST
GND
J3
I/O
GND
J4 STOP
NCN4555
EVALUATION BOARD AND PCB GUIDELINES
Figure 12. NCN4555 engineering test board schematic diagram
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MBRA140T3 GND GND J9 GND J10 GND J11 GND
10
NC 13 CLK SIM_CLK 14 RST SIM_RST 15 I/O SIM_I/O 16 NC GND GND_EXP 1 STOP 2 MOD_VCC 4 NC NC 5 VBAT SIM_VCC
4 C4 3 CLK 2 RST 1 VCC
8 NC C8 7 I/O 6 NC VDD 5 GND SIM_CARD VDD CON2 IP9 R5 R6 POI2 2.2 k
GND
J5
MOD_VCC
NC
NC
SENSE_SIM_V CC
GND
GND
GND Q1 2N2222
12 11 10 9 8 7 6 5 4 3 2 1
J6
CONTROL & I/O
GND
NCN4555
EVALUATION BOARD AND PCB GUIDELINES
Top Layer
Bottom Layer
Figure 13. NCN4555 Printed Circuit Board Layout (Engineering board)
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NCN4555
PACKAGE DIMENSIONS
QFN-16 3*3*0.75 MM, 0.5 P CASE 488AK-01 ISSUE O
D
A B
PIN 1 LOCATION
E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM SPACING BETWEEN LEAD TIP AND FLAG. MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 --- 0.30 0.50
0.15 C 0.15 C 0.10 C TOP VIEW
16 X
0.08 C SIDE VIEW A1 C
16X
L
5 8
NOTE 5 4
16X
K
1 12
16X
0.10 C A B 0.05 C
NOTE 3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
CCC CCC CCC
(A3) D2 e
9 16 13
A
SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
EXPOSED PAD
E2
b BOTTOM VIEW
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NCN4555/D

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